Samsung moves into the era of 3-nanometer chips with nano-chips

Samsung announced the production of its new generation “3 nm” chips, which will soon be available in smartphones and computers. More than size, it’s the geometry of the transistors that really changes, by packing nanosheets to make current flow.

In the ongoing race to miniaturize processors, Samsung has just taken advantage of its competitors. The South Korean heavyweight in consumer electronics announced on June 30, 2022 the start of production of the next generation of chips, bypassing American Intel and Taiwan’s TSMC, two competitors that also participated in this competition.

Samsung’s announcement revolves around the generation of chips that are engraved with a precision of 3 nanometers. On this scale, the thickness of a hair might seem enormous: a nanometer is a tiny fraction of a meter (a billionth) and a hair is 50,000 times thicker. Today, the most advanced chips on the market are advertised in 5 and 7 nanometers (nm).

50,000 times smaller than the thickness of a hair

The Asian giant is full of praise for describing the paradigm shift. Compared to 5 nm, this is the first process of 3 nm” Reduces power consumption by up to 45%, improves performance by 23%, and reduces surface area by 16% With the second generation, the gains are 50%, 30% and 35%, respectively.

Regular advances in advanced computer engineering have the effect of giving the impression of throwing earlier statements on the topic light years away from us. Remember: In 2017, IBM had the pleasure of figuring out how to burn chips at 5nm resolution. Five years later, this level of engraving has become very popular.

And so we find this engraving prowess in Apple (M1, M2, A14 Bionic, A15 Bionic …) Qualcomm (Snapdragon), Samsung (Exynos), HiSilicon (Kirin), Nvidia (Grace Hopper), but also AMD or MediaTek. Today, smartphones and computers are usually equipped with components that take advantage of developments that IBM welcomes.

The schedule for the deployment of this new class of microprocessors was not detailed in the Samsung announcement, but it is likely that we will see this change in 2023. It is time to reach mass production at an industrial rate, in order to provide production lines that will assemble future components for computers and smartphones.

Playing with the geometry of the transistor

It should be noted that the degree of miniaturization has become so severe that various advertisements do not do justice to the developments of recent years. Terms such as 3nm, 5nm, 7nm, but also a few thresholds above, no longer refer a lot to size, but to a particular technology and a certain geometric shape in the design.

Thus, Samsung relies on a technology called ‘GAAFET’ and an in-house solution called ‘MBCFET’. For anyone who doesn’t follow therapist news closely, these abbreviations are ambiguous. It should be noted that since 2010, “3D” processors began to appear, in contrast to traditional “flat” technologies.

Schematic representation of the evolution of transistor engineering, as they are “miniature”. Its structure changes, not necessarily its size. // Source: Applied Materials

Thus the sector began to move to a FinFET (finned field-effect transistor) solution. This process, which transformed the geometry of the transistors, was used to generate 14 nm, 10 nm and 7 nm. Then the ‘GAAFET’ (global gate) method came to go below the 7 nm threshold, in particular 5 nm.

GAAFET is a derivative of FinFET, but is somehow applied everywhere – hence its name The gate is everywhere, to indicate that there are several gates to allow electric current to pass through the transistors – but the difficulty is that everything has become so small that there is a leak of electrons. Hence work on the engineering of the transistors now, not on their size.

With GAAFET, the conduction channel is reduced to nanowires, as detailed in 2019 by Olivier Vaineau, division head at the Atomic Energy Commission (CEA) at the Laboratory of Electronics and Information Technology. Samsung has taken the logic behind the GAAFET process to develop MBCFET (Multi-Bridge-Channel FET).

Nanopapers instead of nanowires at Samsung

With the success, the South Korean founder is proud, because the limits of FinFET performance have been exceeded, both in terms of energy efficiency and performance. the secret ? The nanowires are being replaced by nanowires, which conduct electricity better. Samsung notes that this is a proprietary technology.

Samsung GAAFET
The path taken by Samsung, transistors take on a certain “thickness” – hence the term 3D transistors. // Source: Samsung

Here, nanosheets with larger channels are implemented to achieve the previously mentioned performance. The nanowires and their narrow channels are being replaced and the founder warns that it is also capable of modifying the channel width” To improve energy use and performance to meet different customer needs “.

Samsung’s work is a good example of the fact that the race to miniaturization has somewhat faced a technical wall and manufacturers are forced to come up with original methods to continue improving processors. FinFETs, GAAFETs, and MBCFETs are more proof of this. And Oliver Faneo said nothing else:

The terms used no longer necessarily correspond to a dimension measured on the integrated circuit. Historically, when we talked about the 28 nm node, this value reflected a physical quantity, the gate length of the transistor. From now on, when an industrialist mentions a knot of 5 or 7 nm, the dimensions are instead of 10 nm. »

It is widely recognized in the industry that nanolabels are inconsistent, confusing and do not reflect the latest innovations in transistors.”, announced Chelsea Hughes, a spokesperson for Intel. But it is sometimes difficult to get rid of the marketing, because the group evoked the clip to an “angstroms age” – that is, under a nanometer.

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